1. Technical Field of the Invention
The present invention generally relates to the field of integrated circuit (IC) design and layout verification. More particularly, and not by way of any limitation, the present invention is directed to a layout design process and system for providing bypass capacitance and compliant densities in an IC chip.
2. Description of Related Art
Modern IC technologies require active area and polysilicon densities to be within certain upper and lower bounds. Such technologies typically use fill features involving the active area and/or polysilicon layers in order to achieve density compliance. These fill features, while improving manufacturability of the IC device, offer no electrical advantage. In particular, where stringent minimum bypass capacitance requirements are imposed on a circuit, merely providing electrically inactive fill features is not a viable solution. On the other hand, if a circuit layout is designed with a view to maximize its bypass capacitance, the densities may be out of bounds.
Accordingly, the present invention advantageously provides a layout design process and system for providing bypass capacitance and compliant densities in an IC chip without the aforementioned deficiencies. In one embodiment, an adjustable capacitor cell is provided as a plurality of sub-cells, each with a polysilicon shape disposed over a corresponding active area shape. The polysilicon shapes are electrically coupled to a first power rail and the active area shapes are electrically coupled to a second power rail. The sub-cells of the adjustable capacitor cell are operable to be modified to satisfy a density or electrical measurement associated with the IC.